By Prashant Saxena, Rupesh S. Shelar, Sachin Sapatnekar
This quantity presents a whole knowing of the elemental factors of routing congestion in present-day and next-generation VLSI circuits, bargains options for estimating and relieving congestion, and gives a serious research of the accuracy and effectiveness of those concepts. The publication contains metrics and optimization innovations for routing congestion at quite a few levels of the VLSI layout stream. the topics lined comprise an evidence of why the matter of congestion is critical and the way it is going to pattern, plus definitions of metrics which are acceptable for measuring congestion, and outlines of suggestions for estimating and optimizing routing congestion matters in cell-/library-based VLSI circuits.
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