By Martin Wirnshofer
Expanding functionality calls for in built-in circuits, including constrained strength budgets, strength IC designers to discover new methods of saving strength. One leading edge means is the offered adaptive voltage scaling scheme, which tunes the availability voltage based on the current procedure, voltage and temperature adaptations in addition to getting older. The voltage is customized “on the fly” through in-situ hold up screens to take advantage of unused timing margin, produced through state of the art worst-case designs. This publication discusses the layout of the improved in-situ hold up displays and the implementation of the whole control-loop comprising the screens, a control-logic and an on-chip voltage regulator. An analytical Markov-based version of the control-loop is derived to investigate its robustness and balance. Variation-Aware Adaptive Voltage Scaling for electronic CMOS Circuits offers an in-depth overview of the proposed voltage scaling scheme whilst utilized to an mathematics and a picture processing circuit. This publication is written for engineers drawn to adaptive options for low-power CMOS circuits.
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